Diagrammatic Reasoning for Delay-Insensitive Asynchronous Circuits

In this paper we construct a new trace model of delay-insensitive asynchronous circuits inspired by Ebergen’s model in such a way that it satisfies the compositional properties of a category, with additional monoidal structure and further algebraic properties. These properties taken together lay a solid mathematical foundation for a diagrammatic approach to reasoning about asynchronous circuits, which represents a formalisation of common intuitions about asynchronous circuits and their properties. 1 Asynchronous circuits In the last few decades interest in asynchronous digital design ebbed and flowed. On the one hand, many studies have identified a great promise in asynchronous circuits, in particular low power consumption and modularity. On the other hand problems such as large silicone footprint and difficulties of fabrication hampered the adoption of asynchronous technology into the mainstream. These are just some of the well known advantages and disadvantages of the technology [1]. Another challenge raised by asynchronous design is that of reasoning about the correctness of circuits, and it has attracted a great deal of research interest. Several models of asynchronous circuits exists, such as Huffman [2] and burstmode circuits [3], which fall in the broader category of bounded-delay circuits, and delay-insensitive circuits, of which a notable version are the so-called micropipelines [4]. The bounded-delay model takes explicitly into account the precise propagation delays of signals along circuit paths, or at least bounds on these delays. This is a fairly obvious model, but it has serious disadvantages. The first one is that computing delays is complicated, as propagation delays in a circuit can be data-dependent. The second one is that reasoning needs to be “geometric” rather than “topological”, as wire lengths are highly relevant. This means that accurate reasoning can only be made after a circuit is placed and routed. Because one logical design can have a large number of concrete instantiations (layouts) this low-level way of reasoning is highly undersirable. Far more attractive is the delay-insensitive model, which aims to design circuits that behave well no matter what the delays in the circuit. This is the model we will focus on. Typically, delay insensitive circuits are constructed out of a fixed set of primitive gates. Some of the most common are: C The Muller C-element is the typical synchronisation gate. It produces an output if it receives signals on both inputs. X The exclusive or is a merging gate, which outputs if it receives a signal on either input. T The toggle gate alternates (deterministically or nondeterministically) between the two outputs whenever it receives an input. The forking wire can be seen as a gate which duplicates its input signal. By signal we understand either a high-to-low or a low-to-high change in voltage on a pin. Other more complex gates can be introduced either as primitives or constructed out of these. The main correctness challenge of the design of asynchronous circuits is to avoid so called “glitches”: two signals which travel along the same wire can, if too close to each other, cancel each other out: The reason is that the wires in a circuit are not ideal conductors but have capacitance, which acts like an inertial delay. If the signals are too close, they are “absorbed” by the capacitive inertia. A typical glitchy circuit is the one below: